1. Field of the Invention
The present invention relates to a bus architecture communications scheme for enabling communications between a plurality devices or nodes coupled together in a computer system, and more particularly, to a dynamic, multi-speed bus architecture for enabling multi-speed data transfers on a bus having variable speed and fixed speed nodes connected thereto.
Computer devices or nodes within a given computer system, such as a microprocessor, a disk drive, a CRT, a printer and the like, convey signals between themselves through the use of a bus which normally comprises a plurality of transmission channels and acts as a communications path for interconnecting several nodes in the system. Each node in the system need only plug into the bus to be theoretically connected to each of the other nodes in the system. In this type of bus architecture, a signal which is transmitted on the bus by a particular node is available for reception by all other nodes attached to the bus. However, these bus architectures require that the data transfers be performed at a fixed speed corresponding to the speed of the slowest node so that data signals transmitted on the bus can be received and properly decoded by all nodes coupled to the bus.
In order to overcome this fixed speed requirement, multi-speed bus architectures (both serial and parallel) have been proposed so as to achieve optimum price-performance system implementation and open-ended, upward compatibility. What has resulted from these proposals is a high speed bus architecture which takes advantage of the higher speed capability of the newer nodes coupled to the bus. In such bus architectures, the higher speed nodes transmit data signals at their respective speeds to all nodes irregardless of the speed capability of the receiving nodes. In this way, transmissions between higher speed nodes may be accomplished at faster speeds. However, transmissions between lower speed nodes, or between both higher and lower speed nodes, must occur at a lower speed which is fixed by the slowest node taking part in the transmission. A major problem posed by this type of bus architecture scheme is that in high speed transmissions between higher speed nodes, the lower speed nodes must still be able to detect the beginning and end of the higher speed transmissions so that their timing of the different phases in the protocol for the bus will not be disturbed.
A known solution to this problem is the use of speed messages which are attached to the front end of the data signal transfers and transmitted concurrently therewith. In addition, these "multi-speed busses" also comprise a high speed envelope detector in each of the lower speed nodes coupled to the bus for detecting the length (i.e., the duration) of the data signal transfer. As a data signal is transmitted on the bus, each node decodes the speed message to determine if it can properly receive the transmission. If the node has a lower speed than that of the transmission, this lower speed node cannot decode the transmission, but instead uses the envelope detector to detect the presence and duration of the transmission. This enables the lower speed node to stay in synch with the protocol timing of the bus.
Nonetheless, the use of envelope detectors has its drawbacks; the implementation of the detector circuitry compromises the cost advantage of the lower speed nodes. It also restricts the expandability of the bus in terms of its speed due to the fact that the slowest node coupled to the bus dictates the maximum speed of the data signal transfer on the bus. That is, the bus in all its future implementations cannot transfer data at a speed higher than the maximum working speed of the slowest envelope detector (usually implemented in the earliest nodes). Hence, these so-called "multi-speed busses" are in actuality only high speed busses based on the slowest speed of the slowest node coupled to the bus.
Accordingly, it is an object of the present invention to provide a method and apparatus for the transfer of speed messages on a multi-speed bus independent of the data signal transfers.
Another object of the present invention is to provide a method and apparatus for the exchange of speed messages between adjacent nodes coupled to a multi-speed bus so as to inform the downstream relaying nodes of the transmission speed of a data signal transfer and to inform the transmitting node and all upstream relaying nodes of the speed capability of all the downstream, adjacent nodes.
It is another object of the present invention to provide a multi-speed bus architecture in which higher speed, data signal transfers to lower speed nodes are substituted with low speed, mock signals having the same duration as the data signal transfers so as to enable the use of lower speed nodes which do not require high speed envelope detectors.
A further object of the present invention is to provide a multi-speed bus having upward expandability, wherein the use of present, lower speed nodes in no way limits the capabilities of future high speed nodes and wherein the higher speed signaling mechanism need only be implemented in the higher speed nodes that are going to benefit from it.
Yet another object of the present invention is to provide a method and apparatus for the parallel or concurrent transmission of speed signals or messages with arbitration signals using a common mode signaling technique, which method and apparatus further resolves the problem of a limited common mode voltage range at both the transmitter and receiver ends of the bus.
A still further object of the present invention is to implement the above objects in a multi-speed, serial bus architecture pursuant to the IEEE P1394 standard having an arbitrary bus topology where nodes coupled to the bus need not be arranged in a predefined network topology but can be arbitrarily coupled to other nodes via the serial bus to form an assorted number of network arrangements.